RISC-V is an open, free instruction set architecture (ISA) enabling a new era of processor innovation through open standard collaboration. Under the governance of the RISC-V Foundation, RISC-V offers numerous benefits, including enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Portability is another benefit of the technology.
Born in academia and research (UC Berkeley), RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.